ROM is well known in the art. ROM typically contains instructions or data that are both unchanging and critical for the operation of the electrical device into which it is incorporated. The contents of the ROM dictate the physical structure of the ROM, as the zeros and ones that comprise the ROM's digital contents are realized as functional or non-functional transistors, respectively.
In known ROM fabrication, the contents of the ROM memory have typically been programmed into the ROM using only one process layer. The layer used has been either the diffusion layer, the contact layer, or the via layer.
FIG. 1a is an illustration showing a conventional diffusion programmable ROM memory cell 16a, programmed as a “0” cell. The “0” cell 16a includes a wordline 12 coupled to a diffusion layer 20, a bitline contact 22 coupling the diffusion layer 20 to a bitline 14, and a ground diffusion wire 24 that is coupled to ground.
Initially the bitline 14 is charged high to a logical “1.” As long as wordline 12 is low, bitline 14 remains high because the diffusion layer 20 isolates bitline contact 22 from the ground diffusion wire 24. However, when wordline 12 is asserted high, diffusion layer 20 becomes conductive and bitline 14 is pulled low. Asserting wordline 12 high charges diffusion layer 20 and causes it to conduct, creating a connection between bitline contact 22 and ground diffusion wire 24. As bitline 14 is coupled to bitline contact 22 and thus to ground diffusion wire 24 via diffusion layer 20, bitline 14 is pulled low.
FIG. 1b illustrates a conventional diffusion programmable ROM memory cell 16d, programmed as a “1” cell. The “1” memory cell 16d includes a wordline 12, a diffusion layer 20 separated into a first portion 26a and a second portion 26b, a bitline contact 22 coupling the first portion 26a of the diffusion layer 20 to a bitline 14, and a ground diffusion wire 24 coupling the second portion 26b of the diffusion layer 20 to ground.
Similar to the “0” cell, the “1” memory cell 16d initially has bitline 14 charged high to a logical “1.” As wordline 12 is low, bitline 14 remains high because diffusion layer 20 isolates bitline contact 22 from ground diffusion wire 24. Unlike the “0” cell, the “1” cell allows bitline 14 to remain high when wordline 12 is asserted high. As diffusion layer 20 is removed from around wordline 12, diffusion layer 20 is not charged when wordline 12 is asserted high, and a connection is not formed between bitline contact 22 and ground diffusion wire 24. Bitline 14 is thus never pulled low in the “1” memory cell 16d. 
FIG. 2 is an illustration showing a conventional diffusion programmable ROM memory cell array 30 comprised of two memory cells. Cell array 30 includes a first memory cell 32 and a second memory cell 34. First memory cell 32 includes a first wordline 12a coupled to a diffusion layer 20, a shared bitline contact 22 coupling a bitline 14 to the diffusion layer 20 and a first ground diffusion wire 24a coupling diffusion layer 20 to ground.
Second memory cell 34 shares the diffusion layer 20 with first memory cell 32 and includes a second wordline 12b coupled to diffusion layer 20. Second memory cell 34 also includes shared bitline contact 22 that couples bitline 14 to diffusion layer 20 and a second ground diffusion wire 24b coupling diffusion layer 20 to ground.
In operation, first wordline 12a is utilized to address first memory cell 32 and second wordline 12b is utilized to address second memory cell 34, both of which can affect bitline 14.
For first memory cell 32, bitline 14 is initially charged high to a logical “1.” While first wordline 12a is low, bitline 14 maintains its state, usually high, because diffusion layer 20 isolates shared bitline contact 22 from the first ground diffusion wire 24a. However, when first wordline 12a is asserted high, bitline 14 is pulled low because diffusion layer 20 becomes conductive between shared bitline contact 22 and first ground diffusion wire 24a. 
Asserting first wordline 12a high charges diffusion layer 20 between shared bitline contact 22 and first ground diffusion wire 24a and causes it to conduct, creating a connection between shared bitline contact 22 and first ground diffusion wire 24a. As bitline 14 is coupled to shared bitline contact 22, and therefore also to first ground diffusion wire 24a via diffusion layer 20, bitline 14 is pulled low.
Second memory cell 34 operates in a similar manner. Asserting second wordline 12b high charges diffusion layer 20 between shared bitline contact 22 and second ground diffusion wire 24b and causes it to conduct, creating a connection between shared bitline contact 22 and second ground diffusion wire 24b. As bitline 14 is coupled to shared bitline contact 22 and also to second ground diffusion wire 24b via charged diffusion layer 20, bitline 14 is pulled low.
Current semiconductor processes are complicated undertakings, requiring dozens of steps, each of which steps taking up time and introducing materials handling and inventory factors. Customers expect that the turn-around time or cycle time to be kept as short as possible. Unfortunately, as the code for data and programs stored in the ROM are fixed at the time of manufacture, an error in the ROM code results in wasted ROM wafers. For example, if the ROM includes program code and a bug is later discovered in the program code, wafers containing ROMs are wasted if the wafers have already been processed past the processing step required for programming the ROMs.
For the preceding reason at least, programming is preferably done as late in the manufacturing process as possible. As the diffusion layer must be formed early in the manufacturing process, a diffusion programmable ROM must be programmed early in the manufacturing process. In response to this shortcoming, via programmable ROMs were developed that allow for late process programming.
FIG. 3 is an illustration showing a conventional via programmable ROM cell array 40 comprised of two memory cells. Via programmable ROM cell array 40 includes first memory cell 42 and a second memory cell 44. First memory cell 42 includes a first diffusion layer 20a coupled to a first wordline 12a, a first ground diffusion wire 24a, a first metal to diffusion contact 22a which couples a first m1 pad 46a to drain diffusion 20a of first memory cell 42 and a first m2 to m1 via 22b which couples first ml pad 46a to m2 bitline 14. Similarly, second memory cell 44 includes a second diffusion layer 20b coupled to a second wordline 12b, a second ground diffusion wire 24b, a second diffusion contact 22c, a second m1 pad 46b, and a second m2 to m1 via 22d which couples to bitline 14.
Via-programmable ROM cell array 40 operates similarly to the diffusion programmable ROM cell array discussed previously. In first memory cell 42, when first wordline 12a is low, first diffusion layer 20a is nonconductive and no current flows through first m2 to m1 via 22b to first m1 pad 46a down through first metal to diffusion contact 22a to ground diffusion wire 24a. When first wordline 12a is asserted high, first diffusion layer 20a becomes charged and conductive, forming a conduction path between first metal to diffusion contact 22a and first m1 pad 46a and first m2 to m1 via 22b and diffusion ground wire 24a. As bitline 14 is coupled to first m2 to m1 via 22b via first m1 pad 46a and first metal to diffusion contact 22a, bitline 14 goes low, resulting in a logical “0.” Second memory cell 44 operates in a similar manner.
Both first and second memory cells 42 and 44 are “0” cells because they allow bitline 14 to go low when their corresponding wordline 12a/12b is selected. To make a via programmable ROM memory cell a “1” cell, bitline m2 to m1 via is removed. For example, removing first bitline m2 to m1 via 22b will program the first memory cell 42 to a “1” cell.
As the memory cells in a via programmable ROM are programmed by altering the via layer rather than the diffusion layer, a via programmable ROM can be programmed later in the manufacturing process, when the via layers are formed. In this manner, production can be initiated on a wafer of via programmable ROMs, and held at a later stage in the manufacturing process. Micro-code for the ROMs can be upgraded with a minimal amount of time required to modify the via masks and complete processing of the wafers. Thus, via programmable ROMs provide greater flexibility than diffusion programmable ROMs.
As shown in FIG. 3, bitline contacts 22a/22c, m1 pads 46a/46b, and m2 to m1 vias 22b/22d cannot be shared in the via programmable ROM memory cell array 40. Each memory cell 42/44 must be formed on a separate portion of diffusion, resulting in wasted space 50. More particularly, space 50 between first m1 pad 46a and second m1 pad 46b is wasted. Thus, conventional via programmable ROMs are less dense and larger than conventional diffusion programmable ROMs.
As a result, semiconductor chip designers conventionally had to choose between the flexibility provided by via programmable ROMs and the density provided by diffusion programmable ROMs.
Further, there exist minimum size rules that restrict the size of a piece of diffusion used in semiconductor manufacturing to a predetermined minimum diffusion size, as a result of manufacturing limitations in the semiconductor manufacturing processes. A transistor designed on a very small portion of diffusion will be restricted in practice to using a larger diffusion size if the particular designed size of diffusion is smaller than the predetermined minimum diffusion size.
Thus, each “1” cell of a conventional diffusion programmable ROM requires two separate diffusion zones, each being no smaller than the predetermined minimum diffusion size. Similarly, all memory cells of a conventional via programmable ROM are formed on separate portions of diffusion, each being no smaller than the predetermined minimum diffusion size. Thus, there is a minimum size that conventional programmable ROMs must be.
The contact programmable ROM cell shown in FIG. 4 uses a single diffusion island 51 to create the “0-0” bitcell. A diffusion island cannot be shared across horizontal boundaries when these bitcells are stacked vertically. Contact layer programming is used to connect the source of the bitcell transistors to the metal 1 ground. If the diffusion island was shared across boundaries, the individual programmability would be lost as the diffusion islands would already be connected. This requirement results in a ROM using contact layer programming being larger in area than other known ROMs.
The need for ROM cells of smaller size therefore cannot be met by currently known designs and manufacturing processes.